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te c h t m preliminary t35l3232b taiwan memory technology, inc. reserves the right p. 1 publication date: feb . 2000 to change products or specifications without not ice. revision:0.a synchronous burst sram 32k x 32 sram pipeline and flow - through burst mode features ?e ft pin for user configurable pipeline or flow - through operation. ?e fast access times: - pipeline ? 3.8 / 4 / 4.5 ns - flow - through ? 9 / 10 / 11ns ?e single 3.3v +0.3v/ - 0.165v power supply ?e common data inputs and data outputs ?e individual byte write enable and global write control ?e three chip enables for depth expansion and address pipelining ?e clock - controlled and registered address, data i/os and control signals ?e internally self - timed write cycle ?e burst control pins ( interleaved or linear burst sequence) ?e high 30pf output drive capability at rated access time ?e snooze mode for reduced power standby ?e burst sequence : - interleaved (mode=nc or vcc) - linea r (mode=gnd) options marking - 3.8 -4 - 4.5 access time 3.8ns 4ns 4.5ns pipeline 3-1-1-1 cycle time 6.6ns 7.5ns 8.5ns access time 9ns 10ns 11ns flow- through 2-1-1-1 cycle time 10.5ns 15ns 15ns package 100 - pin qfp q 100 - pin tqfp t part number examples part no. pkg. t35l3232b - 3.8 q q t35l3232b -4t t general description the taiwan memory technology synchronous burst ram family employs high - speed, low power cmos design using advanced triple -layer polysilicon, double -layer metal t echnology. each memory cell consists of four transistors and two high valued resistors. the t35l3232b sram integrates 32,768 x 32 bits sram cells with advanced synchronous peripheral circuitry and a 2- bit counter for internal burst operation. all synchron ous inputs are gated by registers controlled by a positive - edge - triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, address - pipelining chip enable ( ce ), depth - expansion chip enables ( ce 2 and ce2), burst control inputs ( adsc , adsp , and adv ), write enables ( bw 1 , bw 2 , bw 3 , bw 4 , and bwe ), and global writ e ( gw ). asynchronous inputs include the output enable ( oe ), snooze enable (zz) and burst mode control (mode). the data outputs (q), enabled by oe , are also asynchronous. addresses and chip enables are registered with either address status processor ( adsp ) or address status controller ( adsc ) input pins. subsequent burst addresses can be internally generated as controlled by the burst advance pin ( adv ). address and write controls are registered on - chip to initiate self -timed write cycle. write cycles can be one to four bytes wide as controlled by the write control inputs. individual byte write allows individual byte to be written. bw 1 controls dq1 - dq8. bw 2 controls dq9 - dq16. bw 3 controls dq17 - dq 24. bw 4 controls dq25 - dq32. bw 1 , bw 2 , bw 3 , and bw 4 can be active only with bwe being low. gw being low causes all bytes to be written. write pass - through capability allows written data available at the output for the immediately next read cycle. this device also incorporates pipelined e nable circuit for easy depth expansion without penalizing system performance.
te c h t m preliminary t35l3232b taiwan memory technology, inc. reserves the right p. 2 publication date: feb . 2000 to change products or specifications without not ice. revision:0.a functional block diagram note: the functional block diagram illustrates simplified device operation. see truth table, pin descriptions and timing diagrams for detailed in formation. byte 4 write register enable register byte 1 write register byte 3 write register byte 2 write register address register binary counter & logic clr q0 15 15 13 15 a0 a1 a1' a0' 32k x 8 x 4 memory array sense amps input registers 8 8 8 8 8 8 8 8 32 32 32 dq1 ?e ?e ?e dq32 4 a0-a14 mode adv clk adsc adsp bw4 bw3 bw2 bw1 ce ce2 ce2 oe gw bwe q1 output buffers byte 1 write driver byte 2 write driver byte 3 write driver byte 4 write driver ft
te c h t m preliminary t35l3232b taiwan memory technology, inc. reserves the right p. 3 publication date: feb . 2000 to change products or specifications without not ice. revision:0.a pin assignment (top view) nc dq17 dq18 vccq vssq dq19 dq20 dq21 dq22 vssq vccq dq23 dq24 ft vcc nc vss dq25 dq26 vccq vssq dq27 dq28 dq29 dq30 vssq vccq dq31 dq32 nc nc dq1 dq2 vccq vssq dq3 dq4 dq5 dq6 vssq vccq dq7 dq8 zz vcc nc vss dq9 dq10 vccq vssq dq11 dq12 dq13 dq14 vssq vccq dq15 dq16 nc 1 11 10 9 8 7 6 5 4 3 2 18 17 16 15 14 13 12 28 27 26 25 24 23 22 21 20 19 30 29 31 41403938373635343332 4948474645444342 50 60 59 58 57 56 55 54 53 52 51 70 69 68 67 66 65 64 63 62 61 80 79 78 77 76 75 74 73 72 71 9596 88 87 86 85 84 83 82 819091929394 89 100 99 98 97 a7 a6 bwe gw clk vss vcc ce2 bw1 bw2 bw3 bw4 ce2 ce adv adsp adsc oe a9 a8 nc vcc nc nc a10 a0 nc vss a11 a12 a13 a14 nc nc a1 a2 a3 mode a4 a5 100-pin qfp or 100-pin tqfp
te c h t m preliminary t35l3232b taiwan memory technology, inc. reserves the right p. 12 publication date: feb. 2000 to change products or specifications without notice. revision:0.a pipeline read timing high-z burst read c lk ads c a d s p a d d r e s s g w , b w e , b w 1 - b w 4 t kc t kh t kl t adss t adsh don' t care undefined t adss t adsh t as t ah t ws t wh t ces t ceh t aas t aah t oeq t kqx t oelz t oehz t kq t kqhz t kq t kqlz sing le read (note3) q(a1) q(a2) q(a2+1) q(a2+2) q(a2+3) q(a2+1) burst wraps around to its inital state. adv suspends burst. burst continued with new base address. q(a2) a3 a2a1 (note1) deselect cycle. ce ( n o t e 2 ) adv o e q q(a3) t kqx note: 1. q(a2) refers to output from address a2. q (a2 + 1) refers to output from the next internal burst address following a2. 2. ce 2 and ce2 have timing identical to ce . on t his diagram, when ce is low, ce 2 is low and ce2 is high. when ce is high, ce 2 is high and ce2 is low. 3. timing is shown assuming that the device was not enabled before entering into t his sequence. oe does not cause q to be driven until after the following clock rising edge.
te c h t m preliminary t35l3232b taiwan memory technology, inc. reserves the right p. 13 publication date: feb. 2000 to change products or specifications without notice. revision:0.a flow-through read timing note: 1. q(a2) refers to output from address a2. q (a2 + 1) refers to output from the next internal burst address following a2. 2. ce 2 and ce2 have timing identical to ce . on this diagram, when ce is low, ce 2 is low and ce2 is high. when ce is high, ce 2 is high a nd ce2 is low. 3. timing is shown assuming that the device was not enabled before entering into this sequence. oe does not cause q to be driven until after the following clock rising edge. 4. output are disabled t kqhz after diselect. high-z b u r st r e ad c l k ad s c a d s p ad d r e s s g w , b w e , b w 1 - b w 4 t k c t k h t k l t ad s s t a d s h don't care undefined t ad s s t a d s h t as t a h t w s t w h t c e s t c e h t a a s t a ah t o eq t k q x t o el z t o ehz t kq t kq hz t kq t k q lz s i n g le r e a d q (a1 ) q (a2 ) q (a2 +1 ) q (a2 +2 ) q (a2 +3 ) q (a2 +1 ) b ur s t w ra ps a ro und to i t s i n i t a l s t a t e . ad v s us pe n ds bu rs t . q(a2 ) a2 a 1 (note 1 ) c e ( n o t e 2 ) a d v o e q d e s e le c t c y c le ( no t e 4 ) q (a2 +2 )
te c h t m preliminary t35l3232b taiwan memory technology, inc. reserves the right p. 14 publication date: feb. 2000 to change products or specifications without notice. revision:0.a write t iming burst w rite c l k ads c high-z a d s p a d d r e s s b w e , b w 1 - b w 4 t kc t kh t kl t adss t adsh do n' t care undefined t as t ah t ws t wh t ces t ceh t aas t aah t oehz t ds t dh single w rit e (note3) d(a1) d(a2) d(a2+1) d(a2+2) d(a2+3) d(a3+1)d(a3) a3 a2a1 (note1) ce ( n o t e 2 ) adv o e d adsc extends burst. t adss t adsh t adss t adsh g w t ws t wh d(a2+1) d(a3+2) burst read exte nde d burst write q adv suspnds burst. (note4) (note5) byt e w rit e s ignals a re ignored for first cycle when adsp init ialtes bu rst. note: 1. q(a2) refers to output from address a2. q (a2 + 1) refers to output from the next internal burst address following a2. 2. ce 2 and ce2 have timing identical to ce . on this diagram, w hen ce is low , ce 2 is low and ce2 is high. when ce is high , ce 2 is high and ce2 is low. 3. oe must be high before the input data setup and hold high throughout the data hold time. this prevents input/output data contention for the time period to the byte write enable inputs being sampled. 4. ad v must be high to permit a write to the loaded address. 5. full width write can be initiated by gw low or gw high and bwe , bw1 - bw4 low.
te c h t m preliminary t35l3232b taiwan memory technology, inc. reserves the right p. 15 publication date: feb. 2000 to change products or specifications without notice. revision:0.a pipeline read/write timing a4 high-z burst read c l k ads c a d s p a d d r e s s b w e b w 1 - b w 4 t kc t kh t kl t adss t adsh don' t care undefined t as t ah t ws t wh t ces t ceh t dh t kq t oelz t oehz t ds t kq t kqlz single writ e q(a1) q(a2) q(a3) q(a4) q(a4+1) q(a4+3)q(a4+2) a5 a3a1 (note1) ce ( n o t e 2 ) adv o e d a2 a6 q high-z d(a3) d(a5) d(a6) back-to-back reads pass-through read back-to-back writes note: 1. q(a4) refers to output from address a4. q (a4 + 1) refers to output from the nex t internal burst address following a4. 2. ce 2 and ce2 have timing identical to ce . on this diagram, when ce is low, ce 2 is low and ce2 is high. when ce is high, ce2 is high and ce2 is low. 3. the data bus (q) remains in high - z following a write cycle unless an adsp , adsc or adv cycle is performed. 4. gw is high. 5. back - to - back read s may be controlled by either adsp or adsc .
te c h t m preliminary t35l3232b taiwan memory technology, inc. reserves the right p. 16 publication date: feb. 2000 to change products or specifications without notice. revision:0.a flow-through read/write timing note: 1. q(a4) refers to output from address a4. q (a4 + 1) refers to output from the next internal burst address following a4. 2. ce 2 and ce2 have timing identical to ce . on this diagram, when ce is low, ce 2 is low and ce2 is high. when ce is high, ce2 is high and ce2 is low. 3. the data bus (q) remains in high - z following a write cycle unless an adsp , adsc or adv cycle is performed. 4. gw is high. 5. back - to - back reads may be controlled by either adsp or adsc . a 4 b u r s t r e a d c l k ad s c a d s p ad d r e s s b w e b w 1 - b w 4 ( n o t e 4 ) t k c t k h t k l t a d s s t a d s h do n' t care undefined t a s t a h t w s t w h t c e s t c e h t d h t k q t o el z t o e hz t d s s i ng le w r it e q (a1 ) q (a2 ) q (a4 ) q (a4 +1 ) q (a4 +3 )q (a4 +2 ) a 5 a 3a 1 (no te 1 ) c e ( n o t e 2 ) a d v o e d a 2 a 6 q high-z d (a3 ) d (a5 ) d (a6 ) b a c k -t o -b a c k r e a d s b a c k -to -b a c k w r ite s
te c h t m preliminary t35l3232b taiwan memory technology, inc. reser ves the right p. 17 publication date: feb. 2000 to change pro ducts or specifications with out n otice. revision:0.a package dimensions 100 -lead qfp ssram (14 x 20 mm) symbol dimensions in inches dimention in mm a 0.130(max) 3.302(max) a1 0.112 ? 0.005 2.845 ? 0.127 a2 0.004(min) 0.102(min) b 0.012+0.004 - 0.002 0.300+0.102 - 0.0 51 d 0.551 ? 0.005 14.000 ? 0.127 e 0.787 ? 0.005 20.000 ? 0.127 e 0.026 ? 0.006 0.650 ? 0.152 hd' 0.677 ? 0.008 17.200 ? 0.203 he' 0.913 ? 0.008 23.200 ? 0.203 l' 0.032 ? 0.008 0.800 ? 0.203 l1' 0.063 ? 0.008 1.600 ? 0.203 t 0.006+0.004 - 0.002 0.150+0.102 - 0.051 y 0.004(max) 0.102(max) c 0 ?c ~12 ?c 0 ?c ~12 ?c
te c h t m preliminary t35l3232b taiwan memory technology, inc. reser ves the right p. 18 publication date: feb. 2000 to change pro ducts or specifications with out n otice. revision:0.a package dimensions 100 -lead tqfp ssram (14 x 20 mm) symbol dimensions in inches dimention in mm a 0.063(max) 1.600(max) a1 0.055 ? 0.005 1.400 ? 0.050 a2 0.002(min) 0.050(min) b 0. 013+0.002 - 0.004 0.320+0.060 - 0.100 d 0.551 ? 0.004 14.000 ? 0.100 e 0.787 ? 0.004 20.000 ? 0.100 e 0.026 ? 0.006 0.650 ? 0.152 hd' 0.630 ? 0.004 16.000 ? 0.100 he' 0.866 ? 0.004 22.000 ? 0.100 l' 0.024 ? 0.006 0.600 ? 0.150 l1' 0.039 ? 0.006 1.000 ? 0.150 t 0.006 ? 0.002 0.150+0 .050 - 0.060 y 0.003(max) 0.080(max) c 0 ?c ~7 ?c 0 ?c ~7 ?c
te c h t m preliminary t35l3232b taiwan memory technology, inc. reserves the right p. 4 publication date: feb. 2000 to change products or specifications without notice. revision:0.a pin descriptions pins sym. type description 32 - 37, 44 - 48, 81, 82, 99, 100, a0 - a14 input - synchronous addresses: these inputs are registered and must meet the setup and hold times around the rising edge of clk. the burst counter generates internal addresse s associated with a0 and a1, during burst cycle and wait cycle. 93 - 96 bw 1 bw 2 bw 3 bw 4 input - synchronous byte writes: a byte write is low for a write cyle and high for a read cycle. bw 1 controls dq1 - dq8. bw 2 controls dq9 - dq16. bw 3 controls dq17 - dq24. bw 4 controls dq25 - dq32. data i/o are high impedance if either of these inputs are low , conditioned by bwe being low. 87 bwe input - synchronous write enable: this active low input gates byte write operations and must meet the setup and hold times around the rising edge of clk. 88 gw input - synchronous global write: this a ctive low input allows a full 32 - bit write to occur independent of the bwe and bwn lines and must meet the setup and hold times around the rising edge of clk. 89 clk input - synchronous clock: this signal registers the ad dresses, data, chip enables, writecontrol and burst control inputs on its rising edge. all synchronous inputs must meet setup and hold times around the clock's rising edge. 98 ce input - synchronous synchronous chip enable: this active lo w input is used to enable the device and conditions internal use of adsp . this input is sampled only when a new external address is loaded. 92 ce 2 input - synchronous synchronous chip enable: this active low input is used to enable the device. this input is sampled only when a new external address is loaded. this input can be used for memory depth expansion. 97 ce2 input - synchronous synchronous chip enable: this active high input is used to enable the device. this input i s sampled only when a new external address is loaded. this input can be used for memory depth expansion. 86 oe input output enable: this active low asynchronous input enables the data output drivers. 83 adv input - sync hronous address advance: this active low input is used to control the internal burst counter. a high on this pin generates wait cycle (no address advance). 84 adsp input - synchronous address status processor: this active low input, along with ce being low, causes a new external address to be re gistered and a read cycle is initiated using the new address.
te c h t m preliminary t35l3232b taiwan memory technology, inc. reserves the right p. 5 publication date: feb. 2000 to change products or specifications without notice. revision:0.a pin descriptions (continued) qfp pins sym. type description 85 adsc input - synchronous address stat us controller:this active low input causes device to be deselected or selected along with new external address to be registered. a read or write cycle is initiated depending upon write control inputs. 14 ft input - static a low on this p in selects in flow - through mode. a nc or high on this pin selects in pipeline mode. 31 mode input - static mode: this input selects the burst sequence. a low on this pin selects linear burst. a nc or high on this pin selects interleaved burst. do not alter input state while device is operating. 64 zz input snooze enable: this active high asynchronous input causes the device to enter a low - power standby mode in which all data in the memory arry is retained. 2, 3, 6 - 9, 12, 13, 18, 19, 22 - 25, 28, 29, 52, 53, 56 - 59, 62, 63, 68, 69, 72 - 75, 78, 79, dq1 - dq32 input/ output data inputs/outputs: first byte is dq1 - dq8. second byte is dq9 - dq16. third byte is dq17 - dq24. fourth byte is dq25 - dq32. input data must meet setup and hold times around the rising edge of clk. 15,41,65,91 vcc supply power supply: 3.3v +10%/ - 5% 17,40,67,90 vss ground ground: gnd 4,11,20,27,54, 61,70,77 vccq i/o supply output buffer supply: 3.3v +10%/ - 5% 5,10,21,26,55, 60,71,76 vssq i/o ground output buffer ground: gnd 1,16,30,38, 39,42,43,4 9, 50, 51, 66,80 nc - no connect: these signals are not internally conntected.
te c h t m preliminary t35l3232b taiwan memory technology, inc. reserves the right p. 6 publication date: feb. 2000 to change products or specifications without notice. revision:0.a interleaved burst address table (mode = nc/vcc) first address (external) second address (internal) third address (internal) fourth address (internal) a...a00 a...a01 a...a 10 a...a11 a...a01 a...a00 a...a11 a...a10 a...a10 a...a11 a...a00 a...a01 a...a11 a...a10 a...a01 a...a00 linear burst address table (mode = gnd) first address (external) second address (internal) third address (internal) fourth address (internal) a ...a00 a...a01 a...a10 a...a11 a...a01 a...a10 a...a11 a...a00 a...a10 a...a11 a...a00 a...a01 a...a11 a...a00 a...a01 a...a10 partial truth table for read/write function gw bwe bw 1 bw 2 bw 3 bw 4 read h h x x x x read h l h h h h write one byte h l l h h h write all byte h l l l l l write all byte l x x x x x
te c h t m preliminary t35l3232b taiwan memory technology, inc. reserves the right p. 7 publication date: feb. 2000 to change products or specifications without notice. revision:0.a truth table operation address used ce ce2 ce2 zz adsp adsc adv write oe clk dq deselected cycle, power down none h x x l x l x x x l-h high -z deselected cycle , power down none l x l l l x x x x l-h high -z deselected cycle, power down none l h x l l x x x x l-h high -z deselected cycle, power down none l x l l h l x x x l-h high -z deselected cycle, power down none l h x l h l x x x l-h high -z snooze cycle, po wer down none x x x h x x x x x x high -z read cycle, begin burst external l l h l l x x x l l-h q read cycle, begin burst external l l h l l x x x h l-h high -z write cycle, begin burst external l l h l h l x l x l-h d read cycle, begin burst external l l h l h l x h l l-h q read cycle, begin burst external l l h l h l x h h l-h high -z read cycle, continue burst next x x x l h h l h l l-h q read cycle, continue burst next x x x l h h l h h l-h high -z read cycle, continue burst next h x x l x h l h l l-h q read cycle, continue burst next h x x l x h l h h l-h high -z write cycle, continue burst next x x x l h h l l x l-h d write cycle, continue burst next h x x l x h l l x l-h d read cycle, suspend burst current x x x l h h h h l l-h q read cyc le, suspend burst current x x x l h h h h h l-h high -z read cycle, suspend burst current h x x l x h h h l l-h q read cycle, suspend burst current h x x l x h h h h l-h high -z write cycle, suspend burst current x x x l h h h l x l-h d write cycle, susp end burst current h x x l x h h l x l-h d note: 1. x means "don't care." h means logic high. l means logic low. write = l means any one or more byte write enable signals ( bw 1 , bw 2 , bw 3 or bw 4 ) and bwe are low, or gw equals low. write = h means all byte write signal are high. 2. bw 1 = enables write to dq1 - dq8. bw 2 = enables write to dq9 - dq16. bw 3 = enables wri te to dq17 - dq24. bw 4 =enables write to dq25 - dq32. 3. all inputs except oe and zz must meet setup and hold times around the rising edge ( low to high) of clk. 4. suspending burst generates wait cycle. 5. for a write operatio n following a read operation. oe must be high before the input data required setup time plus high - z time for oe and staying high throughout the input data hold time. 6. this device contains circuitry that will ensure the o utputs will be high - z during power - up. 7. adsp = low along with chip being selected always initiates an internal read cycle at the l - h edge of clk. a write cycle can be performed by setting write low for the clk l - h edge of the subsequent wa it cycle. refer to write timing diagram for clarification.
te c h t m preliminary t35l3232b taiwan memory technology, inc. reserves the right p. 8 publication date: feb. 2000 to change products or specifications without notice. revision:0.a absolute maximum ratings* voltage on vcc supply relative to vss. ????- 0.5v to +4.6v i/o supply voltage vccq ........... vss - 0.5v to vcc v in ......................................... - 0.5v to vcc +0.5v storage temperature (plastic)...... - 55 c to +150 c junction temperature ..........?.................. +150 c power dissipation ........................................ 1. 0w short circuit output current...................... 100ma *stresses greater t han those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this spe cification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc electrical characteristics and recommended operating conditions (0 c ta 70 c; vcc = 3.3v +10%/ - 5% unless otherwise noted) description conditions sym. min max units notes input high (logic) voltage v ih 2 vccq + 0.3 v 1, 2 input low (logic) voltage v il - 0.3 0.8 v 1, 2 input leakage current 0v v in vcc i li -2 2 m a 14 output leakage current output(s) disabled, 0v v out vcc i lo -2 2 m a output high voltage i oh = - 4.0 ma v oh 2.4 v 1, 11 output low voltage i ol = 8.0 ma v ol 0.4 v 1, 11 supply voltage vcc 3.1 3.6 v 1 max. description conditions sym. typ - 3.8 -4 - 4.5 units notes power supply current : operating device sel ected; all inputs v il or 3 v ih ; cycle time 3 t kc min; vcc = max; outputs open i cc tbd 250 200 150 ma 3, 12, 13 power supply current: idle device selected; adsc , adsp , adv , gw , bwe 3 v ih ; a ll other inputs v il or 3 v ih ; vcc = max; cycle time 3 t kc min: outputs open i sb1 tbd 60 60 60 ma 12, 13 cmos standby device deselected; vcc = max; all inputs vss + 0.2 or 3 vcc - 0.2; all inputs static; clk frequency =0 i sb2 tbd 10 10 10 ma 12, 13 ttl s tandby device deselected; all inputs v il or 3 v ih ; all inputs static; vcc = max;clk frequency = 0 i sb3 tbd 25 25 25 ma 12, 13 clock running device deselected; all inputs v il or 3 v ih ; vcc =max; clk cycle time 3 t kcmin i sb4 tbd 60 60 60 ma 12, 13
te c h t m preliminary t35l3232b taiwan memory technology, inc. reserves the right p. 9 publication date: feb. 2000 to change products or specifications without notice. revision:0.a ac electrical characteristics (note 5) (0 c t a 70 c;vcc=3.3v +0.3v/ - 0.165v) - 3.8 -4 - 4.5 description sym. min max min max min max units notes clock(pipeline) clock cycle time t kc 6.6 7.5 8.5 ns clock to output valid t kq 3.8 4 4.5 clock to output invalid t kqx 1.5 2 2 ns clock to output in low -z t kqlz 1.5 2 2 ns clock(flow - through) clock cycle time t kc 10.5 15 15 ns clock to output valid t kq 9.0 10 11 clock to output invalid t kqx 3 3 3 ns clock to output i n low -z t kqlz 3 3 3 ns output times clock high time t kh 1.8 1.9 2.0 ns clock low time t kl 1.8 1.9 2.0 ns 6, 7 clock to output in high -z t kqhz 5 5 5 ns 6, 7 oe to output valid t oeq 5 5 5 ns 9 oe to output in low -z t oelz 0 0 0 ns 6, 7 oe to output in high -z t oehz 5 5 5 ns 6, 7 setup times address t as 1.7 2.0 2.0 ns 8, 10 address status( adsc , adsp ) t adss 1.7 2.0 2.0 ns 8, 10 address advance ( adv ) t aas 1.7 2.0 2.0 ns 8, 10 byte write enables ( bw1 ~ bw4 , bwe , gw ) t ws 1.7 2.0 2.0 ns 8, 10 data - in t ds 1.7 2.0 2.0 ns 8, 10 chip enables( ce , ce2 ,ce2 ) t ces 1.7 2.0 2.0 ns 8, 10 hold times address t ah 0.5 0.5 0.5 ns 8, 10 address status( adsc , adsp ) t adsh 0.5 0.5 0.5 ns 8, 10 address advance ( adv ) t aah 0.5 0.5 0.5 ns 8, 10 byte write enables ( bw1 ~ bw4 , bwe , gw ) t wh 0.5 0.5 0.5 ns 8, 10 data - in t dh 0.5 0.5 0.5 ns 8, 10 chip enables( ce , ce2 ,ce2 ) t ceh 0.5 0.5 0.5 ns 8, 10
te c h t m preliminary t35l3232b taiwan memory technology, inc. reserves the right p. 10 publication date: feb. 2000 to change products or specifications without notice. revision:0.a capacitance description conditions sym. typ max units notes input capacitance c i 3 4 pf 4 input/ output capacitance(dq) t a = 25 c; f = 1 mhz vcc = 3.3v c o 6 7 pf 4 thermal consideration description conditions sym. qfp typ units notes thermal resistance - junction to ambient q ja 20 c/w thermal resistance - junction to case still air , soldered on 4.25x1.125 inch 4 - layer pcb q jb 1 c/w ac test conditions input pulse levels 0v to 3.0v input rise and fall times 1.5ns input timing reference levels 1.5v output reference levels 1.5v output load see figures 1 and 2 notes: 1. all voltages referenced to vss (gnd). 2. overshoot: v ih +3.6 v for t t kc/2. undershoot: v il - 1.0 v for t t kc/2. 3. icc is given with no output current. icc increases with greater output loading and f aster cycle times. 4. this parameter is sampled. 5. test conditions as specified with the output loading as shown in fig. 1 unless otherwise noted. 6. output loading is specified with cl = 5 pf as in fig. 2. 7. at any given temperature and voltage conditio n, t kqhz is less than t kqlz and t oehz is less than t oelz. 8. a read cycle is defined by byte write enables all high or adsp low along with chip enables being active for the required setup and hold times. a write cycle is defined by at one byte or all byte write per read/write truth table. 9. oe is a "don't care" when a byte write enable is sampled low. 10.this is a synchronous device. all synchronous inputs must meet specified setup and hold time, except for "don't care" as defin ed in the truth table. 11.ac i/o curves are available upon request. 12."device deselected means the device is in power - down mode as defined in the truth table. "device selected" means the device is active. 13.typical values are measured at 3.3v, 25 c and 2 0ns cycle time. 14.mode pin has an internal pull - up and exhibits an input leakage current of 10 m a. output loads
te c h t m preliminary t35l3232b taiwan memory technology, inc. reserves the right p. 11 publication date: feb. 2000 to change products or specifications without notice. revision:0.a dq 3.3v 317 ohm 351 ohm 5 pf z 0 = 50 ohm 50 ohm vt = 1.5v dq fig. 1 output load equivalent fig. 2 output load equivalent
te c h t m preliminary t35l3232b taiwan memory technology, inc. reserves the right p. 12 publication date: feb. 2000 to change products or specifications without notice. revision:0.a snooze mode snooze mode is a low current, ?power down? mode in which the device is deselected and current is reduced to i zz. the duration of snooze mode is dictated by the length of time the zz pin is in a high state. after entering snooze mode, the clock and all other inputs are ignored. the zz pin (pin 64) is an asynchronous, active high input that causes t he device to enter snooze mode. when the zz pin becomes a logic high, i zz is guaranteed after the setup time t zz is met. any access pending when entering snooze mode is not guaranteed to successfully complete. therefore, snooze mode must not be initiat ed until valid pending operations are completed. snooze mode electrical characteristics description conditions symbol min max units notes current during snooze mode zz 3 v ih i zz 5 ma zz high to snooze mode time t zz 2( t kc) ns 4 snooze mode operation recovery time t rzz 2( t kc) ns 4 snooze mode waveform c l k z z t rzz t zz i z z i supply don' t care ce i s u pp ly note: 1. the ce signal shown above refers to a true state on all chip selects for the device. 2. all other inputs held to static cmos levels (vin vss + 0.2 v or 3 vcc - 0.2 v).

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